SBIR-STTR Award

The goal of the proposed project is to develop regular interferometric based template lithography and demonstrate its feasibility for cost effective, high resolution nanofabrication of low volume electronics. The challenges of the project are based on the requirement to meet the needs of sub-32nm CMOS device fabrication using technologies that are not currently addressed by the ITRS. Design strategies will be developed for the interferometric lithography (IL) imaging system, the integration of the system to a projection lithography (PL) or electron beam lithography (EBL) trim operation, and the identification of suitable processes for template based lithography for 32nm and sub-32nm application. This will be carried out using current design fundamentals of the ASI XIS interference lithography system scaled up to meet CMOS device fabrication needs.

Keywords:
Interferometric Lithography, Template, Trim, Interference, High Resolution

The goal of the Phase II of the project for template IL lithography is to develop a prototype system capable of regular interferometric based template lithography for cost effective, high resolution nanofabrication of low volume electronics to demonstrate the resolution and throughput performance necessary for 45nm lithography generations and beyond. This Phase II proposal will advance of the findings of Phase I of the project to allow for the assembly of a prototype template IL system that will be capable of high resolution, low distortion interferometric patterning. At a numerical aperture of 1.2, the minimum half-pitch geometry will be 40nm, which corresponds to the 32nm technology node. The minimum field size will by 10mm with much less than 50nm of distortion and much less than 100 mWave rms of wavefront aberration. The throughput of the system will be at least 10 wafers per hour.

Keywords:
Template Lithography, Interference Lithography, Deep-Uv, Gridded Design