An emerging class of ultra-low-power applications could have great benefit to the DoD (e.g. wireless sensor nodes, RFIDs, hybrid insects, etc.). Proposed designs of these ULP systems use low voltage sub-threshold operation to reduce energy per operation, but their lifetimes are limited by standby leakage power that is unavoidable when storing data in CMOS memories like SRAM. Integrating a low energy, low voltage, low overhead nonvolatile memory with sub-threshold circuits would greatly improve the flexibility and lifetimes of DoD specific ULP applications. Current nonvolatile memory (NVM) solutions require voltages well in excess of 5V and energy in excess of 5nJ, making them unsuitable for ULP applications. Adesto Technologies has demonstrated a memory cell technology that will be the foundation of an ultra low power nonvolatile memory solution capable of sub 1V with energy per access less than 5pJ, resulting in a 1000x reduction in operational energy. Since the core NVM cell technology is in place, key requirements to realize such ultra low power NVM solutions are appropriate low power circuits and architectures. Phase I funding from SBIR (SB082-045) will allow us to develop ultra low power circuits and architectures for applying our memory technology to ULP sub-threshold applications.
Keywords: Non-Volatile Memory, Sub-Threshold Logic, Sub-Threshold Cmos, Ultra Low Power Electronics, Low Power Memory, Resistive Random Access Memory, Memory Architecture.
