SBIR-STTR Award

LinComp High-Performance Linearity Error Compensator
Award last edited on: 7/2/2010

Sponsored Program
SBIR
Awarding Agency
DOD : DARPA
Total Award Amount
$1,727,013
Award Phase
2
Solicitation Topic Code
SB011-012
Principal Investigator
Scott R Velazquez

Company Information

V Corp Technologies Inc

12526 High Bluff Drive Suite 120
San Diego, CA 92130
   (858) 240-2500
   info@v-corp.com
   www.V-CORP.com,www.vcorptech.com
Location: Single
Congr. District: 52
County: San Diego

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2001
Phase I Amount
$98,943
This Small Business Innovation Research Phase I project demonstrates a breakthrough approach to high-resolution linearity error compensation (LinComp) using computationally-efficient digital signal processing to reduce harmonic and intermodulation distortion in analog-to-digital converters (ADCs), digital-to-analog converters (DACs), sampling circuitry, and radio frequency amplifiers (or the combination of these devices in the complete RF chain) by at least 24 dB. This technology improves the dynamic range by at least four bits, enabling very accurate synthesis of data at high intermediate frequencies (IF) with very high sample rates (e.g., 18-bit dynamic range with 300 MHz sample rate or 12-bit dynamic range at GHz sample rates). The LinComp technology reduces the size, power, and cost of radar systems and RF transceivers by eliminating much of the RF electronics and reducing the digital signal processing requirements. The significant performance improvements afforded by this approach over traditional compensation techniques will be demonstrated in Phase I by implementing the digital processing in realtime FPGA hardware, demonstrating efficient auto-calibration routines, an testing the processor on a combination of devices in an RF chain. The auto-calibration routines will be built in FPGA hardware in the Phase I Option. V-Corp has confirmed the technical efficacy of the LinComp processing methodology by testing with state-of-the-art analog-to-digital and digital-to-analog converters. This compensation approach requires less hardware, provides much better dynamic range, and provides compensation over a wider bandwidth than competing linearity compensation methods (such as phase-plane compensation and dither). Very importantly, the LinComp processor will always exceed the state-of-the-art because it can easily be upgraded as new, more powerful ADC, DAC, and amplifier products become available. During Phase II, a compact LinComp ADC prototype will be developed to enable direct sampling of data at high IF. The LinComp approach overcomes the critical A/D conversion bottleneck which limits performance of state-of-the-art radio frequency transceiver systems. Virtually any high-performance modern electronic system will benefit from the LinComp ADC. Significant applications include enhancement of radar systems, wideband universal RF transceivers, specialized test equipment, and medical imaging systems.

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
2009
Phase II Amount
$1,628,070
This SBIR Phase II project demonstrates a breakthrough approach to high-resolution linearity error compensation (LinComp) using computationally-efficient digital signal processing to reduce harmonic and intermodulation distortion in analog-to-digital converters (ADCs) by up to 24 dB. The core technology can also be used to reduce such distortion in digital-to-analog converters (DACs), sampling circuitry, and radio frequency amplifiers or the combination of these devices in the complete RF chain. This technology improves the dynamic range by up to four bits, enabling very accurate conversion of data at high intermediate frequencies (IF) with very high sample rates (e.g., distortion below -65 dBFS with 1.5 GHz sample rate, direct IF sampling at 1.2 GHz). The LinComp technology reduces the size, power, and cost of radar systems and RF transceivers by eliminating RF downconversion electronics. The highly innovative LinComp processing will be demonstrated in real-time FPGA hardware and fully tested with two different manufacturersÂ’ ADC chips (e.g., MAXIM MAX108, and Atmel AT84AS003), providing 1.5 GHz sample rate, 8 to 10 bit resolution, and direct IF wideband sampling in the second Nyquist zone. The LinComp processing will be implemented in a Xilinx Virtex 4 FPGA. Innovative parallel digital signal processing techniques will be used to provide the full 1.5 GHz data throughput by partitioning the processing into multiple, simultaneous data streams within the FPGA. V Corp has confirmed the technical efficacy of the LinComp processing methodology by testing with state-of-the-art analog-to-digital and digital-to-analog converters. V Corp has executed a highly successful DARPA sponsored SBIR Phase I project demonstrating LinCompÂ’s technical viability. This compensation approach requires less hardware, provides much better dynamic range, and provides compensation over a wider bandwidth than competing linearity compensation methods. Very importantly, the LinComp processor will always exceed the state-of-the-art because it is extremely adaptive and can easily be applied to new, higher performance ADC, DAC, and amplifier products as they become available in the future. V Corp has relationships with many commercial companies such as MAXIM, Raytheon, General Dynamics, Northrop Grumman, and others who have expressed strong commercial interest in LinComp (testimonials included in proposal)

Keywords:
high-resolution, high-speed, linearity compensation, analog-to-digital conversion radio frequency communications, direct IF sampling