We propose an SBIR Phase I program which, through the use of complementary heterojunction bipolar transistor (CHBT) circuits, will extend the sample rate and analog bandwidth of existing silicon analog to digital (A/D) converters by a factor of six. This will be achieved through the design and simulation of CHBT 3 GS/s track and hold circuits with 8 to 10-bit linearity. We will demonstrate how CHBT track and holds can be utilized to produce an 8-bit, 3 GS/s A/D converter with a 1.5 GHz analog bandwidth from a commercially available 8-bit, 500 MS/s A/D converter module with an analog bandwidth of 240 MHz will also be demonstrated. In addition, we will design very high speed CHBT integrated injection logic (I2L) demultiplexers for the purpose of interfacing high speed A/D converters and â¦+ modulators with low speed digital signal processing and memory circuits. These design efforts will be supported by CHBT process characterization and modeling and CHBT device scaling by Research Triangle Institute
