SBIR-STTR Award

P-GILD In Situ Monitor
Award last edited on: 3/15/2002

Sponsored Program
SBIR
Awarding Agency
DOD : DARPA
Total Award Amount
$99,996
Award Phase
1
Solicitation Topic Code
ARPA93-085
Principal Investigator
Dave Markle

Company Information

Ultratech Inc (AKA: Ultratech Stepper Inc)

3050 Zanker Road
San Jose, CA 95134
   (408) 321-8835
   kanderson@corp.ultratech.com
   www.ultratech.com
Location: Single
Congr. District: 17
County: Santa Clara

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
1994
Phase I Amount
$99,996
Projection Gas Immersion Laser Doping (P-GILD) is an innovative technique which merges lithography and doping into a single step process. The result of the merger is a spatially selective process that reduces the process steps required for doping by an order of magnitude. The new process is capable of producing junctions as shallow as 300A" and retrograde profiles having peak to surface doping ratios greater than 10 at depths up to 4000Ao. The technique employs a high power pulsed UV laser to illuminate a dielectric reticle which is imaged onto a wafer in a sealed cell containing a dopant gas at low pressure. The very shallow penetration of the laser light into the silicon surface localizes the heating and results in an extremely low thermal budget that facilitates the use of glass substrates or the construction of multilayer (stacked) circuitry. Good process repeatability requires the development of accurate in situ monitors that directly measure dose and junction depth. We propose to survey candidate monitoring techniques, to determine how the most promising might be implemented, to analytically determine the resulting detection limits and suggest a series of phase II experiments to verify the selected approaches. This will expedite the development of a real time, process controlled, P-GILD technology. Anticipated Benefits/Potential Applications - This program will develop new fabrication tools that will: 1. Reduce cost of fabrication facilities for semiconductor devices and integrated circuits. 2. Produce smaller junction dimensions in semiconductor devices and integrated circuits.

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
----
Phase II Amount
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