The increasing complexity and density of electronic system designs combined with a proliferation of component technologies and choices has created an urgent need for a tool that enables design performance optimization to target criteria (e.g. Speed power, density, area, cost, reliability). While commercial tools are available from synopses and others for this purpose for device level design (e.g. Asics, custom ICS), no such tools are available for multi-device system-level design. In addition, the CAE/CAD tools available today only automate the back-end of the design process: schematic capture, simulation, PCB layout; they do not support design optimization at the front-end of the design process where much of the product life-cycle cost is determined. Based on their eight years of prior work in this area, represented by over 20 publications, omniview's project team members have developed the concept of a design space exploration tool as the performance optimization tool most likely to succeed for technology-independent design synthesis. This approach is derived from twenty man-years of prior development and prototyping work by the team members on micron, an advanced design & synthesis system that automates the front-end of the design process: concept design, partitioning,Component selection, and design integration and re-use. Omniview has been granted an exclusive license to micon technology by Carnegie Mellon University. The proposed tool will enable designers to work at the functional block level, independent of component selection or device technology; enable both structure-preserving and requirement preserving exploration, either user-directed or automatic; and allow performance optimization to the target criteria. Phase I technical objectives include feasibility demonstration of the concept of design-by-functional blocks, development of the architecture and specifications of the design space exploration tool based on a retirement and enhancement of previous work, and definition of the interfaces to families of device technologies and CAE/CAD frameworks, leading to a Phase II implementation and demonstration plan.
