The improvements of the intrinsic device speeds in digital integrated circuit technologies made possible by the reductions in device dimensions (i.e., improved lithography) and other advances of IC technology (including the use of gas or related compound semiconductors rather than silicon) are becoming increasingly difficult to translate into corresponding system performance improvements because of packaging interconnect limitations. While inter-chip signal interconnect propagation delays can be greatly reduced by hybrid wafer scale packaging in which VISI chips virtually tile and interconnect-bearing substrate in a high density Multi-Chip Module (MCM) implementation of the electronic circuitry, the resistivity of normal metal interconnects makes such MCMS extremely difficult to realize in reasonably large sizes (e.g., Carrying many hundreds of high i/o count chips). By using High Temperature Superconductors (HTSCS) for the signal interconnects in the MCM substrate, conductor linewidths of the order of 2um would be useable, allowing the wiring of very complex MCMS with only a few signal interconnect planes that could require so or more normal metal signal interconnect layers. The goal of the proposed study is to, based on the assumption of the development of a practical HTSC MCM technology, a) ididntipy types of system applications which could most benefit from HTSC MCM packaging, b) consider a specific example of an electronics package and evaluate the cost-benefit of upgrading with HTSC MCM technology, and c) identify the CAE tool modifications necessary to make the application of the HTSC MCM technology to real systems practical. Anticipated benefits/potential commercial applications - the development of a practical 80 degrees K HTSC MCM technology, supported by the proper cab tools, will make possible large, high density (e.g., 6 million equivalent gates on a 6" substrate) MCMS.
