The conversion to the use of high-density multi-chip modules to save size, weight and cost, and to reduce signal propagation delays to allow digital systems to realize the performance benefits of the increasing IC clock speeds is well known. Though initial MCMs are smaller, it is clear that mid 1990s MCMs will extend to at least 6" sizes, operating at 100 to 200 MHz clock rates for CMS (much higher for GaAs). A critical problem with these large MCMs is that, while the required interconnect densities require the use of fairly fine line widths (-5 um typically), even when implemented in copper or gold these lines become very attenuating, distortive and slow beyond lengths of a few inches. The use of high temperature superconductors for the signal lines would virtually completely eliminate signal line attenuation at frequencies of interest, even at 1 um line widths (allowing increased densities), plus providing near-perfect shielding for mixed-mode analog/digital MCMs. Currently, however, HTSC films are epitaxially grown on higher substrates, whereas MCMs require a multi-layer interconnect technology with lower dielectrics. The goal of the proposed study is to identified promising technical approaches to fabricating HTSC multi-layer interconnects for high density MCMs or backplanes. Anticipated benefits/potential commercial applications - the development of a practical 80 degree k HTSC multi-layer interconnect technology will make possible large, high density MCMs for high speed CMS or GaAs digital (or mixed-mode) system applications. This technology should see application in a wide range of military systems, as well as commercial products, assuming the availability of efficient, inexpensive 80 degree k refrigerators .Key words: multi-layer, superconducting, interconnects, MCM, high-density, high-speed, packaging, HTSC
