SBIR-STTR Award

Reconfigurable Computer Architecture
Award last edited on: 9/1/2021

Sponsored Program
SBIR
Awarding Agency
DOD : Army
Total Award Amount
$111,457
Award Phase
1
Solicitation Topic Code
A20-100
Principal Investigator
Gary McMillian

Company Information

Crossfield Technology LLC (AKA: SIGNAL_RX~Instrunetix LLC)

3445 Executive Center Drive Suite 125
Austin, TX 78731
   (512) 795-0220
   info@crossfieldtech.com
   www.crossfieldtech.com
Location: Multiple
Congr. District: 10
County: Travis

Phase I

Contract Number: W56HZV-20-C-0178
Start Date: 6/26/2020    Completed: 3/23/2021
Phase I year
2020
Phase I Amount
$111,457
Crossfield Technology proposes a standards-based approach to implementation of reconfigurable Field Programmable Gate Arrays (FPGAs) and System on Chip (SoC) modules that can be rapidly deployed and then upgraded as technology evolves.  FPGA technologies offer the highest degree of programmability and flexibility for functionality and interfaces of all large-scale integrated circuits. With FPGAs set to scale beyond 50 billion transistors, it seems inevitable that interconnecting the logic and memory resources in an optimum manner be a normal part of implementing an algorithm in hardware. In addition, almost any interface can be implemented in an FPGA with an appropriate physical layer device.  Similar to processors with multi-level cache memories, FPGA vendors now provide two or more types of on-die memory. Both FPGAs and processors now provide an option for in-package High Bandwidth Memory (HBM), which offers TB/s memory bandwidth for demanding applications. Unlike processors, though, the memory available to the FPGA fabric can be connected in a manner consistent with the flow of data through the algorithm. FPGAs, and some embedded processors, include multi-protocol transceivers that support common interfaces such as 1/10/40/100G Ethernet, PCI Express, DisplayPort and other serial protocols. The speed of these interfaces are on an upward trend, and are now exploiting modulation techniques such as PAM-4 to increase the Baud rate of each serial lane. It is only a matter of time before 400 Gbps and 1 Tbps links become commonplace. Crossfield is a member of SOSA and VITA, and participated in the recent Tri-Service Open Architecture Interoperability Demonstration (TSOA-ID) event held at GTRI in Atlanta, GA. At the event, Crossfield showcased two OpenVPX payload modules with high-end FPGAs that provide the programmability and many of the interfaces described in this solicitation. Two companion Solid State Memory OpenVPX modules provide 4-16 TB of non-volatile storage. All of the modules have been tested for conformance to their associated HOST Tier 3 Specifications.

Phase II

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Start Date: 00/00/00    Completed: 00/00/00
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