SBIR-STTR Award

Industrial-Quality Porting of the Army's Helios CFD Code into Xeon-Phi-Enabled Systems —A Process-Based Approach for Maximal Speedup
Award last edited on: 3/4/2024

Sponsored Program
SBIR
Awarding Agency
DOD : Army
Total Award Amount
$1,149,981
Award Phase
2
Solicitation Topic Code
A15-102
Principal Investigator
Juan Guillermo Gonzalez

Company Information

Accelogic LLC

1633 Bonaventure Boulevard
Weston, FL 33326
   (954) 888-4711
   info@accelogic.com
   www.accelogic.com
Location: Single
Congr. District: 23
County: Broward

Phase I

Contract Number: W911W6-16-C-0007
Start Date: 4/14/2016    Completed: 7/30/2017
Phase I year
2016
Phase I Amount
$149,993
The recent introduction of Many-Integrated-Core (MIC) architectures such as the Intel Xeon Phi presents an opportunity for enormous performance increases in numerically intensive HPC codes. This project aims at capitalizing on this opportunity by substantially accelerating DoDs CFD solvers by means of maximal utilization of the Xeon Phis resources. In addition to providing increased performance on a DoD code, the proposed work will produce a library of fundamental kernels for exploiting the power of Xeon Phi on CFD applications. The resulting technology will be accompanied by a carefully-planned technology transfer strategy that will maximize the impact of the resulting solvers and tools into Armys strategic missions. The proposed work will leverage Accelogics extensive experience gathered from the acceleration of both Cartesian and unstructured CFD solvers for US Government Agencies. In Phase I we will develop a proof-of-concept prototype that will demonstrate the technologys ability to provide DoDs target acceleration. In Phase II we will work on maturing and refining the technology, driven by a concrete target of accelerating a DoDs High Performance CFD framework. We have secured complementary funds in the amount of $100,000 to ensure that the proposed Phase I work will be successfully accomplished in a timely manner.

Phase II

Contract Number: W911W6-17-C-0026
Start Date: 1/23/2017    Completed: 10/15/2020
Phase II year
2017
Phase II Amount
$999,988
___(NOTE: Note: no official Abstract exists of this Phase II projects. Abstract is modified by idi from relevant Phase I data. The specific Phase II work statement and objectives may differ)___ The recent introduction of Many-Integrated-Core (MIC) architectures such as the Intel Xeon Phi presents an opportunity for enormous performance increases in numerically intensive HPC codes. This project aims at capitalizing on this opportunity by substantially accelerating DoDs CFD solvers by means of maximal utilization of the Xeon Phis resources. In addition to providing increased performance on a DoD code, the proposed work will produce a library of fundamental kernels for exploiting the power of Xeon Phi on CFD applications. The resulting technology will be accompanied by a carefully-planned technology transfer strategy that will maximize the impact of the resulting solvers and tools into Armys strategic missions. The proposed work will leverage Accelogics extensive experience gathered from the acceleration of both Cartesian and unstructured CFD solvers for US Government Agencies. In Phase I we will develop a proof-of-concept prototype that will demonstrate the technologys ability to provide DoDs target acceleration. In Phase II we will work on maturing and refining the technology, driven by a concrete target of accelerating a DoDs High Performance CFD framework. We have secured complementary funds in the amount of $100,000 to ensure that the proposed Phase I work will be successfully accomplished in a timely manner.