SBIR-STTR Award

The primary objective is to provide the concepts and architecture for a real time adaptable ROIC that can be configured dynamically to meet the needs of the application and the real time conditions. Intrinsix will investigate the methods to sense the scene content and to dynamically adjust resolution, frame rate, dynamic range and/or sensitivity as needed to adapt to changing image quality requirements and power consumption needs. The architecture developed would apply to many mobile camera systems including visible, near-IR and short wave IR imaging systems. It will also present a common electrical and physical interface to the larger system. The ROIC design will be scalable in order be used with a variety of array sizes and a range in the pitch of the pixels. Identify Circuit topologies suitable to support programmability for lowering power when warranted by a particular usage mode. Work will build upon efficient topologies used on previous projects. Use Matlab and Simulink to model expected performance. This will be achieved by leveraging: • Intrinsix’s experience with ROICs and A/D converters • Significant R&D expenditures on the use of configurable SDMs. • The serpentine SDM ROIC designed under AF SBIR 093-160

Keywords:
Readout Ic, Image Sensors, Sdm, Focal Plane Array, Visible-Near Infrared, Dynamic Range, Short Wave Ir

There are two objectives of this effort: 1) demonstrate an adaptable, scalable and dynamically configurable digital ReadOut-Integrated-Circuit (ROIC) architecture and 2) establish the foundation for the successful transitioning of this technology to product. This new technology is important because the performance of the ROIC can now be optimized for several different applications in contrast to present technologies where optimal ROIC performance is application specific. With this technology, optimized performance of a ROIC, includes the ability to adapt to different pixel pitches, scale to different detector sizes (rows and columns of pixels) and dynamically make power and performance trade-offs based on an applications requirements. The adaptable and scalable capability of this ROIC technology is based on the concept of a data slice (DS) while the dynamic configuration capability is based on the ability trade-off the performance and power of an SDM analog-to-digital convertor (ADC). The circuit design of the DS is modular and is built from a library of components that are rearranged but not redesigned. This design methodology enables lower cost custom digital ROICs with shorter design cycles compared to a traditional approach.

Keywords:
Roic, Ir, Fpa, Sdm, Adaptable, Scalable, Dynamically Configurable, Hybridization