The Phase II program will demonstrate the Nano-Device Memory Platform (NDMP) 1K memory arrays at 10E10 bits/cm**2 with integrated memory support circuits. A prototype NDMP system will be developed, fabricated, and tested that demonstrates a read-write-erase function over 100,000 cycles with 12 months of non-volatility.
Keywords: Memory Arrays, Silicon Crossbar Technology, Molecular Switches, Information Technology Devices, Manufacturing Engineering