SBIR-STTR Award

Due to factors such as the increasing performance demands placed on IEW systems operating in more sophisticated threat environments, as well as the relatively small acquisitions of IEW systems, the costs of production and operations and support tend to become very substantial in an era of shrinking budgets. However, by suitably exploiting their totally digital nature, many, if not most, of the overlapping digital processing functions presently being performed in different ESM/ECM systems using different digital technology and specialized, custom hardware can be effectively multiplexed within a common digital processor. Virtual digital architectures which can successfully be used to perform the required functions of signal analysis, data processing, display generations, jamming control, and waveform synthesis are evaluated to determine the overlapping commonalities in IEW function. The feasibility of using mostly commercial-off-the-shelf hardware and standardized software packages, with relatively few specialized cards, is explored in considerable depth since the minimization of custom hardware and software requirements is the key to substantially reducing both acquisition and logistics support costs, thereby establishing both the technical and economic feasibility of the concept.

Keywords:
INTELLIGENCE ELECTRONIC WARFARE DIGITAL SIGNAL PROCESSING ESM/ECM

During Phase I, the performance requirements, technological feasibility, and potential cost benefits of a common processor which can replace multiple, application specific processors in IEW systems were quantitatively established. By replacing many custom IEW devices, the common IEW processor can greatly reduce the logistics burden attributable to the many types of complex electronic systems required to support the digital battlefield. Our Phase II program will continue the design and development of the "virtual architectures" and the reconfigurable hardware which enable the common IEW processor (CIP-1) to successfully emulate the high performance, application specific devices. A prototype CIP-l will be designed, fabricated, and tested in an IEW system to fully demonstrate the concept. The prototype design will then be revisited to arrive at the final CIP-l design for fabrication and implementation in IEW and other systems. The product being developed will be able to replace many application specific LRUs in IEW and other government systems where logistics burdens are approaching insupportable levels. The reconfigurable product will also have direct applications in commercial systems, and in reducing product development times.

Keywords:
Digital Processing Reconfigurable Hardware Fpga Intelligence Electronic Warfare