Radar detection of weak targets in the presence of a high level of clutter necessitates an ultra wide bandwidth Analog-to-Digital converter (ADC) with sufficient resolution. This proposal presents a technical approach and system architecture for an 8-bit, 2 GHZ full scale bandwidth integrating ADC to satisfy this need. Additionally, the ADC will be driven by a clock signal which can be synchronized to a trigger pulse with a resolution of +/- 0.5 picoseconds. Such an ADC would facilitate the development of a coherent-on-receive UWB (ultra wide bandwidth) radar receiver. What is proposed is a "flash" ADC architecture, with fast ACT (acoustic charge transport) samplers on the front-end, and slower, commercially available 8-bit ADCs on the back-end. Two embodiments are described. One necessitates using the ACT device as a serial to parallel converter in addition to a sampler and realizes 8 bits of ADC system resolution. The other does not require any serial to parallel shifting but achieves only 6 bits of resolution.
Benefits: The importance of a fast and accurate ADC to the competitive position of the U.S. in the world market for microelectronics cannot be overestimated. ADCs are the key building blocks in a host of commercial systems that range from scientific instrumentation like High energy Physics particle detectors to advanced signal processing system like HDTV (high definition TV).
