We propose to investigate innovative architectures for the economical production of high resolution, high speed dac's without the extreme process control and hand triming now required. Since the goal is to develop, eventually, 1 ghz, 14 bit resolution dac's, the implementation must be realized in gaas as opposed to silicon. However, the problem of maintaining process uniformity and process control in gaas processing does not immediately lend itself to the fabrication of precision components. We propose to address each sourch of dac error or performance degradation systematically and either minimize its effect or, preferably, eliminate it by circumventing the problem totally through architectural redesign. At the same time we will investigate innovative architectures like a segmented ladder approach that would directly affect performance. In particular, we will investigate a novel technique to increase system bandwidth while at the same time leading to a significant reduction in glitch energy at the output of the dac. This technique is described in the main body of this proposal. Additionally, we propose to implement the best design practices for minimizing sources of error like data skew, ground noise, layout induced noise, superposition error, etc.
