Phase II year
2019
(last award dollars: 1688732645)
Phase II Amount
$3,861,874
Recently, the traditional techniques for improving clocked digital logic performance (such as device scaling) has encountered significant limitations. Theseus Logic is commercializing a unique technology that facilitates system level integrated circuit design without the timing derived limitations of traditional clocked techniques. NULL Convention Logic⢠- provides a new and fundamentally more expressive "language" for the design of digital circuits and systems. At the system level, NCL provides circuits which are inherently clockless, delay insensitive, and expressionally complete. Under this SBIR, Theseus intends to design, fabricate, and test an NCL FPGA which validates the routing versus macrocell structures investigated under Phase I. Atmel is a partner in this development and the demonstration device will be based upon the Atmel AT40K FPGA. This reduces the overall program cost since the routing, I/O, and programming software has been previously developed by Atmel.
