SBIR-STTR Award

Hardware Modeler Replacement for Digital Device Simulation
Award last edited on: 3/31/2023

Sponsored Program
SBIR
Awarding Agency
DOD : AF
Total Award Amount
$895,688
Award Phase
2
Solicitation Topic Code
AF172-005
Principal Investigator
Larry V Kirkland

Company Information

WesTest Engineering Corporation

810 West Shepard Lane
Farmington, UT 84025
   (801) 451-9191
   bobl@westest.com
   www.westest.com
Location: Single
Congr. District: 02
County: Davis

Phase I

Contract Number: FA8100-18-C-0006
Start Date: 12/5/2017    Completed: 12/5/2018
Phase I year
2018
Phase I Amount
$145,736
Many custom and hybrid integrated circuits (ICs) and custom electronic components cannot bemodeled in simulation software because of their complexity and/or lack of technical data.TPS developers need to use a hardware modeler for these types of integrated circuits.The proposed WesTest Hardware Modeler will be compatible with LASAR and the VDATS Di-Series digital subsystem.It utilizes the Teradyne Di-series digital subsystem in conjunction with the Teradyne LASAR simulation software to model digital, hybrid and custom ICs and the circuit boards in which they are installed to produce fault dictionary and guided probe diagnostics for the VDATS Test Station.The hardware modeling system will have the ability to model multiple devices (both dynamic and static devices) simultaneously. It will be able to retain input (stimulus) and output patterns for entire clock cycles, and therefore, reestablish the state of the device under simulation in a repeatable manner.VDATS TPS developers and maintainers can benefit greatly from the WesTest Hardware Modeler by using the actual Teradyne Di-series digital hardware to perform the simulation. This type of simulation is performed on the actual test equipment used for the TPS so accurate simulation results are achieved.

Phase II

Contract Number: FA8100-19-C-0006
Start Date: 5/6/2019    Completed: 5/6/2021
Phase II year
2019
Phase II Amount
$749,952
Many custom and hybrid integrated circuits (ICs) and custom electronic components cannot be modeled in simulation software because of their complexity and/or lack of technical data. The current hardware modeler (D300) in conjunction with the Teradyne LASAR digital simulator has the ability to perform this modeling. The hardware modeling system has the ability to model multiple devices (both dynamic and static devices) simultaneously. It is also able to retain input (stimulus) and output patterns for entire clock cycles, and therefore, reestablish the state of the device under simulation in a repeatable manner. WesTest proposes using of the VDATS Di-Series digital subsystem hardware as a replacement for the D300 hardware. WesTest shall develop a solution that can replace the Teradyne D300 DATASource Hardware Modeler with the WesTest D3000 DEVICESource Hardware Modeler System which utilizes the VDATS TERADYNE Di-digital subsystem hardware. The new WesTest D3000 DEVICESource Hardware Modeler System will replace the obsolete D300. This concept solution addresses software interfaces, hardware interfaces and estimates of LASAR simulation run times using the VDATS Di digital subsystem hardware. Also, the solution includes the device/chip socket concepts, the device hardware model file concepts, LASAR devise model files, receiver interface, pin-map layout. etc.