SBIR-STTR Award

Low-Latency Embedded Vision Processor (LLEVS)
Award last edited on: 4/1/2019

Sponsored Program
STTR
Awarding Agency
DOD : AF
Total Award Amount
$149,972
Award Phase
1
Solicitation Topic Code
AF15-AT13
Principal Investigator
Wesley Sheridan

Company Information

SAGE Technologies

1601 North Sepulveda Boulevard Pmb501
Manhattan Beach, CA 90266
   (310) 374-4374
   info@sagetechnologies.com
   www.sagetechnologies.com

Research Institution

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Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2015
Phase I Amount
$149,972
The proposed VPHS (Vision Processor for Helmet Systems) is an advanced technology image processing engine that is designed to provide the image processing requirements of helmet mounted imagery systems. The VPHS will input high resolution image data from imaging sensors, process that data to yield enhanced visualization and output the imagery to operator displays. The VPHS will employ imaging algorithms to provide for digital fusion of the sensor imagery and other sophisticated image processing functions. The VPHS will support sensor resolution up to 2560 x 2048 formats and up to 96Hz frame rate with less than 1 frame latency. The unit will specifically target minimum SwaP to meet helmet mounted system requirements. The approaches of generating the VPHS consist of low and high risk methods. The low risk method employs near term and emerging technologies. The high risk method projects and innovates new architectures and technology implementations to achieve the performance goals.

Benefits:
The VPHS will be developed primarily for man portable applications with the helmet systems being the primary application. The advanced technology image processor will support hosting the most sophisticated image processing algorithms, affording users the ability to “see” at night and during periods of impaired visibility. The technology is projected to provide a general purpose application architecture, and with minimal impact on the size, weight and power requirements of the target systems. The open source nature of the VPHS will allow it to be adapted and integrated into a host of system and applications environments. The VPHS will initially be targeted for DoD system applications due to cost and technology restrictions.

Keywords:
SWIR, SoC, Acadia II, FPGA, DSP, imaging algorithms, embedded firmware

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
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Phase II Amount
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