SBIR-STTR Award

This project will investigate the feasibility of an integrated multilevel system for protecting space assets from system hardware and firmware exploitation. The overall strategy is to provide greater collective system protection as a whole than would otherwise be available from the sum of the independent defenses. Rather than relying on a loose-knit collection of isolated point solutions that independently address specific hardware and firmware attack vectors, this project will investigate a coherent joint solution where multiple countermeasures work together to better protect an embedded system. The approach is to integrate co-operative firmware execution monitoring, interface mediation, logic configuration monitoring and electrical parameter measurement. The proposed work includes the adaptation of established and developing technologies as well as the development of a covert communication mechanism that facilitates defensive cooperation among the participating countermeasures.

Benefit:
This approach will better facilitate the use of lower cost off shore COTS devices in space-based embedded systems by increasing confidence that all levels of the firmware and hardware design are exploit-free. By detecting pre-deployment exploits it will reduce the cost of re-establishing a pristine design. It will also significantly reduce the cost of post-deployment exploit amelioration. Although this project specifically addresses space-based embedded system applications, there are a broad range of terrestrial commercial applications to which it could also be applied. Any critical terrestrial application of embedded and deeply embedded systems, for example, SCADA and Internet communication systems could also benefit from the results of this work.

Keywords:
Supply Chain, Cots, Space Assets, Embedded System, Firmware Protection, Hardware Protection, Logic Protection, Trojan Detection

The objective of this work is to demonstrate a prototype of an innovative method to protect military space microelectronics from unauthorized tampering. The method will employ the joint cooperation of multiple countermeasures that operate at several levels of system abstraction. The target is a class of embedded systems that are implemented using high-density FPGAs. A dual-use commercial network security system will be prototyped to demonstrate this new protective solution. This prototype will be readily adaptable for military ground as well as aerospace applications.

Benefit:
This work brings the benefits of a defense-in-depth strategy to embedded cyber warfare. It will introduce a novel network security appliance that is, itself, secured from potential COTS component exploits. It will prepare this technology for deployment into an existing government network application. It will demonstrate this technology in a practical ground-based application in preparation for deployment into aerospace- and ground-based military applications. This project will bring the COTS exploit countermeasure technology investigated during Phase I from TRL 3 to TRL 7.

Keywords:
Supply Chain Risk Management, Malicious Hardware, Hardware Trojans, Firmware Trojans, Fpga Viruses, Microelectronics, Counterfeiting, Reliability Impairment