SBIR-STTR Award

This Small Business Innovation Research Phase I project demonstrates a wideband, wide dynamic range, adaptively controlled digital receiver architecture that is dynamically reconfigurable to optimize the performance for the current signal environment. The architecture takes advantage of several, proprietary, high-performance digital signal processing techniques to trade off bandwidth, resolution (SFDR and/or SNR), and power. These techniques can be changed on-the-fly for different operating modes or as signal conditions change. One technique, called Adaptive Parallel Combining (APC), uses a parallel array of high-speed, high-resolution analog-to-digital converters (ADCs) with adaptive signal combining to dramatically improve resolution (both SNR and SFDR) of the digitization while maintaining very high sample rate. A complementary technique, called Advanced Filter Bank (AFB) also uses an array of ADCs, but it greatly improves the bandwidth of the digitization while maintaining high resolution (e.g., four converters can be used to quadruple the bandwidth). Additional techniques include: linearity compensation to improve SFDR and increase analog input bandwidth; averaging of multiple ADCs to improve SNR; channel extraction to zoom in on a desired narrowband; channel matching to digitize multiple channels (e.g., antenna elements) with finely-matched gain and phase; and accurate I/Q demodulation. Using heuristic analysis techniques, this architecture dynamically activates the appropriate DSP techniques to provide optimal performance for the current mode of operation (e.g., for very wideband spectrum monitoring, the AFB and linearity compensation techniques can be used; alternatively, for zooming in on narrowband channels, the APC, averaging, and channel extraction techniques can be used to provide extremely high-resolution). This approach also supports simultaneous outputs (e.g., a wideband, lower-resolution signal for detection and a simultaneous narrowband, high-resolution signal for data analysis, both sharing the same exact same ADC hardware but simultaneously employing different DSP functions). The V Corp proprietary techniques have been proven to provide the highest speed, highest resolution analog-to-digital conversion available currently or in the foreseeable future (similar techniques have already been customized for and implemented in several next-generation communications receivers, RADAR systems, and SIGINT receivers). During Phase I, V Corp will demonstrate the capabilities and functionality of the wide dynamic range digital receiver architecture with adaptive control using data from state-of-the-art ADC chips using V Corp’s advanced DSP techniques to show beyond state-of-the-art performance (e.g., doubling or quadrupling the bandwidth of state-of-the-art digitization, improving the SNR and SFDR by 24 dB with linearity compensation and adaptive parallel combining). During Phase II, a real-time hardware prototype will be implemented.

Benefit:
This dynamically reconfigurable approach overcomes the critical digitization bottleneck which limits performance of state-of-the-art radio frequency transceiver systems. Many high-performance modern electronic systems will benefit from these techniques. Significant applications include enhancement of RADAR systems, SIGINT receivers, wideband universal RF transceivers, specialized test equipment, and medical imaging systems.

Keywords:
High-Resolution, High-Speed, Adaptive, Digital Receiver, Radio Frequency Communications, Radar

This SBIR Phase II project will demonstrate a highly innovative, high-performance Adaptive Digital Receiver architecture with adaptive background control that optimizes the performance in rapidly changing signal environments and provides 2 GHz instantaneous bandwidth, SFDR>90 dB, SNR = 66 dB, with dynamic digital channelization. The efficacy of this technology was proven in the highly successful SBIR Phase I portion of this project. This represents a breakthrough in wideband, high-resolution adaptive digitization and provides receiver performance well beyond current state-of-the-art. The V Corp Adaptive Digital Receiver takes advantage of several levels of adaptivity that the competing approaches do not offer. In addition to a dynamic channelizer that is adaptively tuned based on detected signals, the V Corp approach also includes a powerful Software Reconfigurable Digitizer that is adaptively optimized for the current signal environment to control important receiver parameters such as bandwidth, dynamic range, resolution, and sensitivity. An Open Architecture approach to the prototype system will be used to readily allow the inclusion of existing and future AFRL algorithms. The prototype hardware/software platform will be designed to be highly flexible to accommodate growth of the algorithms and integration with AFRL technologies. The approach uses an array of state-of-the-art converters and takes advantage of several V Corp proprietary, high-performance digital signal processing techniques to trade off bandwidth, dynamic range, resolution, and sensitivity. The Signal Detection algorithm uses techniques such as statistical, spectral, and wavelet analysis to identify the location, bandwidth, level, and modulation type of signals of interest and jammer/interference signals. The Adaptive Real-Time Control Algorithm uses heuristic and iterative approaches to tune the dynamic digital Channelizer and to select the appropriate DSP algorithms for the current conditions. The V Corp dynamic Channelizer uses an efficient polyphase filter bank structure to provide multiple channelized outputs with arbitrary and independent center frequency, bandwidth, gain, and cut-off characteristics. The powerful signal processing technologies can be changed on-the-fly without disruption of the receiver’s normal operation to effectively track signal conditions as they change. One technique, called Adaptive Parallel Combining (APC), uses a parallel array of high-speed, high-resolution analog-to-digital converters (ADCs) with adaptive signal combining to dramatically improve resolution (both SNR and SFDR) of the digitization while maintaining very high sample rate. A complementary technique, called Advanced Filter Bank (AFB) also uses an array of ADCs, but it greatly improves the bandwidth of the digitization while maintaining high resolution (e.g., four converters can be used to quadruple the bandwidth). Additional techniques include: LinComp linearity compensation to improve SFDR and increase analog input bandwidth; averaging of multiple ADCs to improve SNR; channel extraction to capture a desired narrowband; channel matching to digitize multiple channels (e.g., antenna elements) with finely-matched gain and phase; and accurate I/Q demodulation. The V Corp proprietary techniques have been proven to provide the highest speed, highest resolution analog-to-digital conversion available currently or in the foreseeable future (similar techniques have already been customized for and implemented in several next-generation communications receivers, RADAR systems, and SIGINT receivers). During Phase II, V Corp will demonstrate the capabilities and functionality of the Adaptive Digital Receiver architecture with dynamic channelization and adaptive control with a hardware prototype using V Corp’s advanced DSP techniques to show beyond state-of-the-art performance. BENEFIT

Keywords:
High-Resolution, High-Speed, Adaptive, Digital Receiver, Radio Frequency Communications, Radar, Cognitive Radio