SBIR-STTR Award

As the US DOD and other agencies continue to undertake ever-challenging missions, the performance of space On-Board Processing (OBP) is often the limiting factor on what is achievable for a given mission objective.  To meet this demand, the defense industry as a whole has increasingly incorporated advanced technologies to bridge the performance gap brought on by increasing sensor data production, limited downlink capacity, and the need for real-time battlespace situational awareness.  The use of Field-Programmable Gate Arrays (FPGAs) have contributed significantly in increase performance, but drawbacks such as radiation susceptibility, power consumption, floating-point processing overhead, and a challenging programming model make them suboptimal solutions for many critical DoD aerospace missions.  Multi-core processing architectures show significant potential to address this performance gap.  MAESTRO is a 49-core processor under development by Boeing using Radiation-Hardened by Design (RHBD) techniques funded by the NRO On-board Processing Expandable Reconfigurable Architecture (OPERA) program.  The program is only funding for the development of the OPERA processor, and for Phase I, SEAKR proposes to lay the groundwork for developing a flexible MAESTRO space qualified On-Board Processing (OBP) system.

Benefit:
As the US DOD and other agencies continue to undertake ever-challenging missions, the performance of space On-Board Processing (OBP) is often the limiting factor on what is achievable for a given mission objective.  To meet this demand, the defense industry as a whole has increasingly incorporated advanced technologies to bridge the performance gap brought on by increasing sensor data production, limited downlink capacity, and the need for real-time battlespace situational awareness.  The use of Field-Programmable Gate Arrays (FPGAs) have contributed significantly in increase performance, but drawbacks such as radiation susceptibility, power consumption, floating-point processing overhead, and a challenging programming model make them suboptimal solutions for many critical DoD aerospace missions.  Multi-core processing architectures show significant potential to address this performance gap.  MAESTRO is a 49-core processor under development by Boeing using Radiation-Hardened by Design (RHBD) techniques funded by the NRO On-board Processing Expandable Reconfigurable Architecture (OPERA) program.  The program is only funding for the development of the OPERA processor, and for Phase I, SEAKR proposes to lay the groundwork for developing a flexible MAESTRO space qualified On-Board Processing (OBP) system.

Keywords:
On-Board Processing, Fpga, Radiation-Hardened By Design, Expandable Reconfigurable Architecture, Opera, Multi-Cell Processor, Data Processing

The MAESTRO Phase II SBIR’s focus is the design and build of a single board processor based on the MAESTRO chip developed by the U.S. Government. The board will be on a commercial VPX (Vita-46) 6U standard. The processor chip used on the board is a multi-core processor, with 49 identical processing cores, 4 banks of DDR2 memory, and 4 XAUI 10Gb interfaces. The VPX standard supports interfaces up to 40Gbps. The processor board will be designed as a prototype software development station for use by the MAESTRO community. The development includes an initial board support package, hardware and software documentation and porting of a software application from the phase I SBIR for validation of throughput.

Benefit:
The MAESTRO board has a number of applications, both terrestrial and space based. The initial prototype board will be used as a software development station for algorithmic development. The prototype board can be used as a verification vehicle for radiation testing and characterization of the MAESTRO processor itself. The board uses a powerful multi-core processor that has been developed using rad-hard by design libraries, and can be spun into a flight version for space applications.

Keywords:
Multi-Core Processor, Maestro, Rad-Hard Processor, Vpx, Vita-46, Polymorphic Computing