SBIR-STTR Award

This proposal describes an innovative radiation hardened by design approach for improving integrated circuit reliability while minimizing impact on area overhead, power consumption, and electrical performance degradation over indigenous libraries. The approach is based on an innovative built in current sensor (BICS) technique designed to provide portability across alternative foundries, newly developed processes, and diverse combinational and sequential digital, analog, and mixed signal design architectures including full custom, semi custom, standard cell, and programmable array integrated circuits. The BICS approach will be characterized and validated against a standard set of metrics, including design, area overhead, performance, and power consumption, and will determine its efficacy within a system integration recovery (SIR) environment developed by L3, our DEC teammate. Phase I will include simulation and modeling of feasible designs, process variations, subthreshold leakage, radiation effects, and reliability monitor. Design portability will be investigated for digital/analog full custom, semi custom, standard cell, and programmable array architectures. These results will become the baseline research for a transition into a Phase II contract. With the effective modeling and simulation approach conducted in Phase I, the Phase II project will develop the detailed design, fabricate and validate the BICS solution set.

Keywords:
Radiation Hardened By Design (Rhbd), Current Sensor, Integrated Circuit, Reliability Monitor, Space Communications, Space Computer, Avionics, Single Event Effects

This proposal describes an innovative reliability defect detection and fault propagation approach for improving integrated circuit reliability while minimizing impact on area overhead, power consumption, and electrical performance degradation over indigenous libraries. The approach is based on an innovative built in current sensor (BICS) technique designed to provide portability across process independent foundries suitable for digital, analog, and mixed signal design architectures. The BICS approach will be further characterized and validated against a standard set of metrics, including design, area overhead, performance, and power consumption, and further characterized as prototypes in silicon. Phase I included simulation and modeling of feasible designs, process variations, subthreshold leakage, radiation effects, and reliability monitor. These results provided baseline results for a Phase II research effort focusing on validating the theoretical results. A Phase II project will provide various detailed designs, layouts, and parts fabricated using a 180nm Bulk CMOS process to further validate the BICS solution set. The BICS designs will be used to determine its efficacy within a plug and play System Integrated Recovery (SIR) environment being developed by L-3/Jaycor, our collaborative partner.

Benefit:
Results from this successful research will lead to a cost effective reliability enhanced design (RED) technique for improving reliability of present and future space electronics, especially for space computers. Furthermore, the approach is ideally suited for present, as well as future, ultra large-scale integration (ULSI) integrated circuit (IC) designs based on ultra deep submicron processes. The technique overlays seamlessly in present day IC designs as a supplemental in-circuit reliability monitor for commercial and military electronics. The BICS possesses unique attributes enabling it to become increasingly more effective as circuit densities are increased and feature sizes scaled below 90nm making it ideal for plug and play architectures in operationally responsive space applications.

Keywords:
Radiation Hardened By Design (Rhbd), Current Sensor, Integrated Circuit, Reliability Monitor, Space Communications, Space Computer, Avionics, Single E