To improve design reliability and reduce errors and error-testing, Starbridge intends to add a high-level architecture entry capability to its upcoming Viva design entry application. This will provide a standardized method of entering specifications for large-scale systems. In addition, Viva will provide full verification to ensure that the system meets its operational goals. Once the design has been implemented in a digital system, the intended results will be compared to the hardware signals to ensure accuracy and timing integrity. These capabilities will both simplify FPGA development and provide greater assurance that the device will function as desired.
Keywords: Reconfigurable Computing, Digital Design, Circuit Modeling, Automatic Test Equipment, Software, Design Verification, Vhdl, Fpgas
