An overdue standardized and programmable chip level approach will move Space based DSP into ultra-efficient frequency domain vector processing and allow high resolution, high sample rate, and multi-dimensional signal and image processing with minimal power dissipation and minimal software engineering. Current DSP processors take a "business" computing microprocessor architectural approach to DSP, ignoring the complex vector and data flow nature of digital signal processing applications. Our approach centers DSP around a unique multi-dimensional FFT centric structure that scales almost endlessly through cascading identical step and repeat macro library building blocks while maintaining signal precisions of 24 bits binary and beyond. By applying deterministic data flow techniques and a latency insensitive system approach our processors will efficiently maximize the final DSP resolution, precision, and sample rate of any chip geometry required by an application. Additionally, our chips can signal process "stand alone" or look like simple high level instruction set extensions to any host microprocessor, allowing the host to do what it does best simultaneously in parallel with the signal processing.
Benefits: Commercial applications such as software defined radio, ultra-wide bandwidth wireless communications, and 3-D virtual reality image processing will have a new tool that promises a dramatic leap in performance and signal intelligence.
Keywords: polyphase filtering, FFT, DSP, rad hard DSP, multidimensional DSP, frequency domain, low latency DSP, high performance DSP
