SBIR-STTR Award

Novel radiation-hardened synchronous pipelined multibank fault-tolerant static-random- access-memory (SRAM) will be developed. The SRAM will combine high speed performance and radiation-hardness with high packing density, low power consumption and manufacturability at reasonable costs. Unique circuits and circuit organization, i.e. self- compensating current-sense, voltage limiters, parameter-tracking references, self-adjusting logic, shuffle, error corrector and fault-masking circuits, will contribute to narrow or close the speed-gap between radiation hardened SRAMs and the digital-signal-processors DSPs. Fault- tolerance will be used only to the level that satisfies the requirements. In Phase I, the architecture and the key circuits and a test-chip concept will be developed, in Phase II a complete SRAM will be designed, fabricated and evaluated, and in Phase III modified SRAM designs will be commercialized. The outcome of this effort will be key elements in future defense systems, commercial satellites, cosmic missions, nuclear weapons, power sources, propulsion devices and in other radiation hardened ambiences.The anticipated results of this research and development program can lead to a breakthrough in the implementation of an advanced national defense-system. Namely, the proposed SRAM is a key element that can satisfy the elevated requirements in operational speed and radiation hardness. The private industry would progress in obtaining high-reliability fast SRAMs for applications in extreme environments

The objective of this project is to produce complementary-metal-oxide-semiconductor (CMOS) static-random-access memories (SRAMs) which combine very high operational speed, radiation hardness, amenability to emdedded silicon-on-chip (SOC) applications, high packing density, low power consumption and manufacturability at reasonable costs. The technical approach is based on radiation hardened circuit-modules which are used to create SRAM-circuit organizations for dual, i.e. military and commerical, applications. Novel algebraic multiplicative, synchronous multibank, shuffle and associative repair circuit organizations, and innovative hardened memory cell, self-compensating current sense amplifier, multiple-error detector and corrector and fault masking component circuits, are to provide short access times and fault-tolerence in radiation environments. In Phase I the feasibility of the novel circuit organizations and component circuits were convincingly demonstrated, in Phase II test-chips and complete military SRAMs will be designed, fabricated and evaluated, and in Phase III modified SRAM designs will be commericalized. The outcome of this effort will be elements in future defense systems, satellites, nuclears weapons, power sources, propulsion devices and in other DoD and civilian systems and equipment