SDV proposes to investigate the development of productivity enhancing tools for the comparison of re-engineered clone VHDL models with Legacy Avionics Hardware modules. This would be accomplished by the semi-automatic generation of additional functional test vectors. The proposed tool would identify VHDL constructs that have not been exercised during functional simulation. Additional test vectors would be created to exercise these constructs, as well as to propagate the response from these vectors to the module boundary. The response of the Legacy Hardware to these additional test vectors would be learnt and an enhanced VHDL testbench would be constructed which would be applied to the VHDL model to ensure its functional accuracy. The proposed tool would aim to substantially reduce rather than eliminate the requirement for skilled VHDL professionals during this clone validation process. Phase I objectives are to assess the feasibility of this approach and to assess the productivity enhancements to be derived from use of this solution. Anticipated Benefits/
Potential Commercial Applications:Reduced cost of re-engineering Legacy Avionics Hardware to prolong service life of systems which contain obsolete electronic components. Development of commercial tools to reduce the cost and increase the quality of ASIC's and other complex digital semiconductors.
