SBIR-STTR Award

IKOS Systems proposes to integrate a high performance, IEEE VHDL WAVES input-output capability into their VHDL mixed-level simulation environment. This will enhance WAVES ability to effectively support large, complex digital electronic designs. The interface will have two elements. First, a Compiler for WAVES data into a compact binary format for input into both the VHDL simulation engine and the gate level simulation accelerator inside the IKOS's VHDL mixed-level simulation environment. This will offer the user the choice of running IEEE WAVES within the VHDL kernel, or as a more efficient, compiled binary format that will be directly injectable into the simulation environment at run time. Second, a Generator that will output simulation result vectors in a WAVES data set format. This will improve the ease of WAVES creation, debug, and transport. These two mechanisms form the foundation for run time execution of IEEE WAVES simulation data within a commercially viable VHDL product that has the performance and capacity required for large and complex electronic system designs. The Phase I objectives are to validate the technical feasibility of this approach, and to produce the preliminary design concepts for the WAVES Compiler and WAVES output generator.

Keywords:
(Waveform/Vector Exchange Standard) (Waveform/Vector Exchange Standard) Ieee Waves Ieee Waves

This research will satisfy a requirement for a high performance, VHDL standard stimulus input and output response format inside a commercially available simulation environment. IKOS Systems is a high-performance system simulation and verification tool supplier to the high-end technology chip design industry. To complement this simulation environment, and offer a commercially available solution for WAVES digital stimulus and response, the new IKOS VHDL mixed-level simulation Environment includes WAVES capability as part of the Flow. The interface will consist of : first, a mechanism for creating large test vector stimulus data sets in WAVES format using the graphical user interface easily and quickly. Second, a compiler for WAVES input data in compact binary format for simulation in the VHDL simulation engine and gate level simulation accelerator inside IKOS' VHDL mixed-level simulation environment. This will offer the designer the choice of running WAVES within the VHDL kernel in purely behavioral code, or in the more efficient, compiled binary format that is directly injectable into the mixed-level simulation environment at run time. Third, a Generator that will output simulation response in the WAVES data set format. This wil improve the ease of WAVES creation, debug, and transport. These mechanisms form the foundation for run time execution of WAVES simulation data within a commercially viable VHDL product that has the performance and capacity required for large, complex electronic systems designs

Keywords:
Waves Usability Waves Subset Checking Waves Output Generation Waves Test Bench Development Waves Sim