SBIR-STTR Award

The design, simulation, fabrication, and testing of a parallel digital signal processor (DSP) chip that can be programmed to execute parallel algorithms in the guidance, surveillance, remote sensing, inspection, medical imaging, video compression, and image processing (2-D and 3-D) on data from multiple sensors is the goal of this project. The DSP chip will contain many processors and low latency interprocessor connection network based on segmented-switched buses for fast communication. Novel parallel algorithms in the above areas will be analyzed to determine the instruction set of a processor in the DSP. A pipelined and low-power architecture will be designed for the processor and simulated. Each processor will have its own simple sequence controller and memory for data and instructions. We intend to put 64 processors, memory for the processors, and the interconnection between the processors in a single chip. The processors will be designed to operate in the multiple instruction and multiple data stream (MIMD) or single program and multiple data stream (SPMD) mode of parallel computing. During Phase I, the architecture of the DSP will be designed and an instruction level simulator completed to predict performance. Macro cells needed to design a low-voltage/low-power DSP chip will be developed and laidout. A floorplan of the DSP chip will also be outlined with area and power consumption estimated using the University of California (UC), Berkeley's Hyper systhesis tools. UC Berkeley's Ptolemy rapid prototyping and simulation system will be used in simulation and hardware/software codesign. During Phase II, the DSP chip layout, fabrication, testing, and demonstration of application programs in the 3-D image processing will be completed. The processor will be implemented using the Hyper and Lager VLSI tools of UC Berkeley and fabricated using USC/ISI MOSIS facility in 0.8 micron CMOS.

Keywords:
PARELLEL DIGITAL SIGNAL PROCES3-D IMAGE PROCESSING HYPER SYNTHESIS TOOLS LAGER SILICON ASSEMBLY TOO

The goal of Phase II is to design, simulate, layer, fabricate, and test a low-power parallel DSP chip delivering 3 GOPS and dissipating no more than two Watts using an 0.8 micron CMOS process with three levels of metal offered by the MOSIS foundry facility. The initial design of the processor architecture developed in Phase I will be enhanced and implemented using a low-power semi-custom VLSI technology. The DSP chip will contain 64 processors organized as clusters of eight processors. Each cluster will have segmented-switched buses for fast communication. Connection between clusters will also use buses. Novel schemes will be used to communicate data and programs to the processors. Communication ports for connecting many chips on a board using interconnection networks will also be supported. Each processor will have its semantics. The processors will operate in the multiple instruction and multiple data stream (MIMD) or single program and multiple data stream (SPMD) mode of parallel computing. The chips can be programmed to execute parallel algorithms in the guidance, surveillance, remote sensing, inspection, medical imaging, video compression, and image processing (2-D and 3-D) on data from multiple sensors. University of California (UC), Berkeley's Hyper synthesis tools, low-power design and analysis tools, and Lager VLSI design tools will be used in the design and simulation of the low-power chip. The entire chip will be simulated and fabricated using the USC/ISI's MOSIS foundry brokerage facility on an 0.8 micron CMOS process. Scalable systems using dies of the chip can be constructed for some of the computation intensive (>50 GOPS) realtime applications. The DSP chips will be integrated into a hosted parallel processing system and commercialized during Phase III.

Keywords:
PARALLEL DIGITAL SIGNAL PROCESSOR, 3-D IMAGE PROCESSING, HYPER SYNTHESIS TOOLS, LAGER