The Air Force and other DoD organizations are continuously developing new electronic components for their weapons and other systems. In this effort they are in need of tools to aid in the automated design, or synthesis, of these components. One component of particular importance is the computer processor. It is of enough importance that the Air Force has established a standard for this device (MIL-STD-1750A). The research proposed here applies a new processor synthesis technique, based on the methods of RISC computer design, to the synthesis of the Air Force's 1750A processor. This technique will automatically generate, from a single instruction set architecture specification of the 1750A, different implementations optimized for different applications, with the different implementations based on the instruction frequencies of the applications. Phase I of the proposed research will involve proof-of-concept tests of the synthesis technique and the development of a plan for constructing a robust tool implementing the technique. During Phase II the tool will be constructed, evaluated, and demonstrated. Furthermore, reference manuals and user guides will be developed and training provided to USAF personnel in its use.
