SBIR-STTR Award

Optical architectures are needed for representing and manipulating three-dimensional data objects in a database environment. A class of architectures based on arrays of optical logic devices interconnected in free space will be studied with the expectation that these systems will be commercially viable in the next few years. For this class of architectures, signal skews do not accumulate for more than one level of logic so that free-space delay provides a storage medium. The use of free-space storage reduces optical power requirements while introducing only a small delay in storage and retrieval of data objects. Manipulation of 3-D objects such as translation and rotation is simplified with this class of architectures because optical signals travel orthogonal to the device substrates, which relieves pinout constraints imposed by alternative approaches. Practical considerations of the optical systems limit storage density, speed, space-bandwidth product, and other characteristics, which will be studied in phase I. Manipulation of spatial optical objects addressed in phase I includes visulaization, creation, projetion, joining and other common database operations.

The Phase I SBIR effort resulted in the gate-level design of a Gaussian elimination processor that solves systems of linear equations and resulted in the finding that design restrictions such as (1) uniform logic operations, (2) simple regular interconnects, and (3) small fan-ins and fan-outs do not by themselves pose severe limitations on digital optical processor performance, but taken in conjunction these restrictions do in fact reduce overall performance, primarily in increased latency and increased gate count. The Phase II effort proposes the development of novel optical interconnection technology that relaxes the fan-in/fan-out and regular interconnection constraints. The development of this interconnect technology is coordinated with the design and fabrication of mask sets for an all optical digital processor that is being designed and built in the Photonics Center at Rome Laboratory/Griffiss AFB. The Phase I Gaussian elimination architecture will be modified to correspond with the interconnection technology that results from this Phase II effort. The anticipated results from the Phase II effort are a viable optical interconnection technology for a digital optical processor, and a physical design for an optical Gaussian elimination processor that utilizes this interconnection technology.