Fast and efficient error detection is the cornerstone in developing a fault tolerant system. Under current program, galaxy has developed an error tolerant CPU architecture that will real time detect and correct soft errors in the registers. Expansion of this work will lead to integrity checking of the remaining processor functions i.e. ALU, I/O, control, etc. Necessary for onboard message processing. This program will define the techniques to implement a real time fault detection/correction single chip processor/controller with online high fault coverage. The overheads associated with the techniques are minimal. The CPU implementation is compatible for gallium arsenide technology providing high performance, radiation hardness, low power, and small die size.
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