SBIR-STTR Award

Binary cyclic redundancy check codes, known as crc codes, are utilized as message error detection codes in applications requiring very highconfidence that a message is received error free. Often, it is assumed that the probability of undetected error for these codes is upper bounded by 2(-r), where r is the number of redundant (parity) bits. This upper bound is not correct for many codes, however, especially shortened cyclic codes. We have found a new method for determining an exact evaluation of the probability of undetected error for the most commonly utilized codes. We propose to investigate how this method can beutilized to produce the very best message error detection codes.

Cyclic Redundancy Check (CRC) codes have become the accepted method of insuring the integrity of messages that have been transmitted over a noisy communications channel. CRC codes with R parity bits are expected to have a probability of undetected error better than 2(-R). Unfortunately many CRC codes do not satisfy this requirement. In this proposal we propose to build two hardware devices for checking the probability of undetected error for CRC codes. The first checker checks CRC codes with a particular form for their generator polynomials for a random error channel. The second hardware device would test general CRC codes for errors caused by arbitrary channels (which might include error correcting coders and decoders). The ultimate aim of these devices is to certify CRC codes to guarantee their performance in real communication environments.