SBIR-STTR Award

The purpose of the proposed program is to design an electro-optic system that will allow the rapid parallel processing of integrated circuits (ics) with focused laser beams. Current laser pantograph (lp) systems, which have been used to successfully fabricate or modify ics, usea single focused beam to scan the ic. This process is too slow to beof significant commercial use. The goal of the proposed program is to design an electro-optic mask that allows numerous focused laser beams (~100) to simultaneously irradiate the ic and thus greatly speed up the laser writing process to the point where it offers benefits over conventional ic fabrication methods for some applications. Several electro-optic systems, developed in other programs, will be investigated for application in the lp field. These spatial light modulators will be analyzed so that they can be rated according to complexity, availability of hardware, cost, laser damage, risk, and processing rate potential. The most attractive concept will be redesigned to satisfy the 100 spot deflection goal of the program. The concept will be fabricatedand tested in phase ii.

Current Laser Pantography (LP) systems, which have been used successfully to fabricate or modify Integrated Circuits (ICs), use a single focused beam to scan the IC. This process is too slow to be of significant commercial use. The goal of the proposed program is to build and test a system which uses a Ferroelectric Liquid Crystal (FLC) Spatial Light Modulator (SLM) to form beams with a desired complex intensity profile. This pattern will then be deflected by an acousto-optic deflector and imaged to the desired region of the IC. In this way, the LP processing rate can be increased by one to two orders of magnitude since numerous controlled points simultaneously irradiate the IC. An FLC SLM with 100 pixels will be purchased commercially and integrated into a beam train for LP testing. In addition, the computer software will be developed for controlling the SLM and acousto-optic deflectors and modulators needed to fabricate the ICs from specs. The intensity pattern generated by the SLM will be characterized by imaging it on a number of photosensitive materials (film, photoresist) prior to actual integrated circuit processing. After initial testing of the apparatus, it will be delivered to Lawrence Livermore National Laboratory for more thorough testing and complex IC fabrication. Since this second round to device characterization will be supported by LLNL's own funding, it will allow for a more detailed test program than would otherwise be possible with SBIR funding. During Phase III of the program, the rapid LP system will be fabricated and sold to companies and institutions with an interest in manufacturing custom chips or rapidly interconnecting a large number of conventionally fabricated chips.