Future Avionics Systems will require capabilities in computing power, performance, and reliability that are not currently available. The Phase I effort identified Wafer Scale Integration (WSI) as a leading candidate for these applications. However, the methods and models for reliability, yield and plan redundancy for WSI circuits are inadequate. Similarly, the models for reliability, thermal and stress analysis are not refined for WSI. New WSI design methods and tools will be needed to support the design of the next-generation fault-tolerant avionics architectures. The proposed WSI simulator will aid in yield prediction and redundancy planning and will evaluate various parameters that affect wafer scale architecture, performance, reliability, availability, and cost. The critical parameters include signal delays, wafer yield, defect tolerance, dynamic fault-tolerance, heat removal capability, and mechanical integrity. Since the importance of these effects is magnified for WSI circuits, new techniques will be developed to estimate their impact for various WSI configurations and to select the optimum configuration. A tradeoff program will be developed to optimize these parameters and thereby to improve wafer yield. Dynamic fault-tolerance simulation capability will also be provided to estimate the effect of operational faults and to predict the reliability of WSI
