SBIR-STTR Award

The ever increasing need for higher performance microcomputer components capable of satisfying real time computational requirements in current and future missile, re-entry, and post-boost vehicle applications are real and demanding necessities. Currently available technology is being taxed to the limits of its performance capabilities especially in the area of nuclear hardness. Estimates of future nuclear requirements place many projected systems and their missions in jeopardy. This SBIR program intends to provide a generally useful, fast, nuclear hard microcomputer through a proposed design and development effort aimed at implementing a 1750a computer chip set in gallium arsenide. Gallium arsenide is an inherently hard, very fast, semiconductor material which will provide an order of magnitude OR more improvement in hardness and performance levels. This development should ultimately lead to the production of a microcomputer chip set which yields a vast improvement in both nuclear hardness and computational power applicable for military as well as commercial markets.

This proposal addresses the need for a radiation hard SEU tolerant MIL-STD-1750A chip set for missile and space applications. The Semiconductor technology approach is to utilize the radiation attributes of gallium arsenide integrated circuits. Nuclear effects capability of Giga-Bit Logic gaAs devices are presently undergoing Evaluation byJacor, (>100 mega-rad total dose capability is anticipated). The chip set construction approach is to utilize as a core chip the gaAs 1750a presently under development by galaxy microsystems under air force contract sponsorship (RADC). This is a single chip implementation of the instruction set architecture for a full-up 1750A. The chip additionally required ROM and RAM which are available from giga-bit gaAs and a Cache Memory Controller (CMC). This proposal covers in part the design of a CMC. The cpu is being implemented so as to include Error Detection And Correction (EDAC) capability which potentially provides a 14 order of magnitude improvement to Single Event Upsets (SEUS). This proposal covers in part the implementation of galaxyis edac techniques into the cmc. To evaluate the application of these techniques and gaAs technology, a test chip under development by galaxy under air force sponsorship (RADC) will be made available for processing and nuclear effects evaluation by Giga-Bit and Jaycor, respectively.