Novel intelligent fault-tolerant semiconductor memory circuits for future mass data storage devices are proposed for research and development. The intelligent features will include self-test, self Repair, internal bookkeeping, self-organization and security keyed Operation. The fault-tolerancy will use a three-level correction System: hard error correction by an electrically programmed substitution system, soft error correction by error checking and correcting codes and yield improvement by laser programmable associative Repair circuits. The objective of this project is to provide CMOS memories which combine very high reliability, density, radiation -hardness, performance, very low power dissipation and high yield. The primary aim is to develop a 1.7 x 10 to the 9th power bit mass storage devices for a minimum of 7 years maintenance-free space operation as replacements for mechanical magnetic tape recorders. Nevertheless, the fault-tolerancy and a novel non-volatile memory cell will allow also for applications in extreme environments, e.g. nuclear weapons and nuclear reactors. Thus the outcome of this effort will be key elements of space defense systems, airborne robots and controls. The increased performance will fill a gap of commercial memory applications in future 5th generation computing systems.
