Company Profile

NanoWatt Design LLC (AKA: NanoWatt Design Inc)
Profile last edited on: 3/29/17      CAGE: 6EXG8      UEI:

Business Identifier: Fast, low-power, integrated circuit architecture
Year Founded
2011
First Award
2013
Latest Award
2015
Program Status
Inactive
Popularity Index
Is this YOUR Company?
Ensure accuracy and completeness of YOUR Company Profile by completing the brief Survey Instrument attached
Do you know about this Awardees?
Let us encourage you to provide any data which would enhance the completeness of this firm's profile.

Location Information

700 W Research Center Boulevard Suite 1620 M/S 2500
Fayetteville, AR 72701
   (479) 527-6510
   N/A
   www.nanowattdesign.com
Location: Single
Congr. District: 03
County: Washingto

Public Profile

NanoWatt Design holds exclusive license to a patent-pending asynchronous circuit architecture that promises order-of-magnitude reductions in power consumption of digital circuitry, without sacrificing speed. The new Sleep Convention Logic (SCL) technology is fundamentally delay insensitive, overcoming timing issues with previous asynchronous architectures. In addition, the company will provide designers with software that allows industry-standard tools to be used in creating asynchronous SCL circuits. Overall, the technology is poised to become the most important integrated circuit design breakthrough of the decade. NanoWatt Design™was formed to commercialize asynchronous circuit architectures. The company has multiple, asynchronous, architectures providing opportunities for reduction in both active and standby leakage power consumption of digital circuitry. The company has capability for implementing Sleep Convention Logic (SCL), Bundled Delay (BD), and Globally Asynchronous Locally Synchronous (GALS) architectures. NanoWatt Design has developed a software tool that extends industry standard design tools for use in automated conversion of circuits from synchronous to asynchronous. The technology solutions are protected by combination of issued and pending patents. Several of NanoWatt’s solutions make use of standard cell libraries, allowing easy introduction into the design process. SCL makes use of a custom library, and promises >20x reduction in standby leakage power. The company is currently focused on bringing to market an ultra-low power, multi-core, digital signal processor (DSP). The DSP makes use of NanoWatt’s patent-pending approach to allow each core to operate independently, using a clock that is not synchronized to the clock of other cores. With this approach, power is saved since each core can operate “just as fast as it must”. Representative smart pad applications. Applications for asynchronous circuits include: LOW POWER, HIGH SPEED devices such embedded video and image processors having dedicated, well-defined workloads. LOW POWER, LOW SPEED devices such as Smart cards, RFID, environmental and agricultural monitoring, (i.e. drought, insects, contamination), homeland security (i.e. border motion, radiation sensing), wild-land fire prediction & detection, AND medical implants. Advantages of NanoWatt Design’s asynchronous circuit solutions include: Multi-core operation optimized by first allowing each core to operate with an independent clock, then reducing voltage and frequency. Optionally, every logic gate “put to sleep” following each operation, and only awakened to respond to data. This is a key advantage for low duty cycle applications. Delay insensitive circuits seamlessly transition from high speed, ultra-low power to low speed, even-lower power, as supply voltage is dropped. Performance (speed) is comparable to synchronous circuits. Compatible with readily available EDA tools developed for synchro

Extent of SBIR involvement

User Avatar

Synopsis: Awardee Business Condition

Employee Range
1-4
Revenue Range
Less than .5M
VC funded?
No
Public/Private
Privately Held
Stock Info
----
IP Holdings
1-4

Awards Distribution by Agency

Most Recent SBIR Projects

Year Phase Agency Total Amount
2015 1 AF $149,999
Project Title: Low-Latency Embedded Vision Processor (LLEVS)
2013 1 NSF $150,000
Project Title: Multi-Core Sleep Convention Logic Processor

Key People / Management

  Ronald B Foster -- CEO

  Jerry Frenkil -- VP of Engineering

  Calvin Goforth -- Chairman of the Board

  Parviz Palangpour