With the increasing complexity of the modern semiconductor supply chain and increasing prevalence of the fabless manufacturing model, the hardware security and design integrity of integrated circuits are threatened by untrusted components such as hardware Trojans. BlueRISC proposes an automated EDA toolkit that utilizes existing Design-For-Testability (DFT) structures (e.g. scan-chains) to enable the identification of hardware trojans during post-manufacturing testing via novel power-correlation analyses. Going beyond this active HW Trojan-centric DFT, the proposed toolkit also enables the identification of malicious circuitry in 3rd party IP during design-time by supporting static power-correlation analyses directly on gate-level netlists and post-physical design databases.
