Future high-performance integrated circuits in DoD satellite systems will require silicon-on-insulator (SOI) and non-planar nano-technology devices, such as MultiGate Field Effect Transistors (MuGFETs) or FinFETs, which can decrease pattern area of logic circuits below 50% of the conventional planar technologies. However, the single-event-effect (SEE) response of non-planar devices and circuits is unknown. To enable characterization and mitigation of SEEs in such technologies, CFDRC, in collaboration with Vanderbilt University (VU) and SEMATECH, is developing the following innovations: (a) First ever characterization, by modeling and experiments, of SEEs in nano-scale SOI and non-planar devices and circuits, including floating body effects and isolation-volumes related charge collection mechanisms; (b) New semiconductor physics models for the nano-technologies: microscopic charge generation in insulators, electron/hole transport in various insulators and insulator-silicon interfaces, implemented in CFDRCs NanoTCAD 3D/mixed-mode simulator; and (c) Simulation-supported design and validation of mitigation techniques for SEEs. In Phase I, representative advanced FinFET and SOI devices and circuits were successfully used for proof-of-concept modeling, validated with experimental data, and characterized for SEEs by means of 3D/mixed-mode simulations. In Phase II, we will perform computational and experimental studies to quantify the floating body and isolation volume related mechanisms, and implement improved models in the NanoTCAD simulator. SEE mitigation methods will be explored, verified, and demonstrated.
Keywords: Non-Planar Nano-Technology Integrated Circuits, Silicon-On-Insulator (Soi) Technology, Multigate Field Effect Transistors, Mugfet, Finfet, Radiation Effects, Single-Event Effe
