SBIR-STTR Award

Room Temperature Implementation of Quantum Algorithms using Spintronics Technology
Award last edited on: 10/20/21

Sponsored Program
STTR
Awarding Agency
NSF
Total Award Amount
$256,000
Award Phase
1
Solicitation Topic Code
QT
Principal Investigator
Behtash Behin-Aein

Company Information

QCML Labs LLC

108 Spinning Wheel Court
West Lafayette, IN 47906
   (765) 586-5936
   N/A
   N/A

Research Institution

Purdue University

Phase I

Contract Number: 2035962
Start Date: 9/1/21    Completed: 8/31/22
Phase I year
2021
Phase I Amount
$256,000
The broader impact of this Small Business Technology Transfer (STTR) Phase I project will be to enable cheaper, faster, and more energy-efficient semiconductor chips dedicated to solving challenges with many possible outcomes and inherent uncertainty. Such problems are encountered in decision-making, risk management, chip design, drug design, business analytics, machine learning, computing failure rates of manufactured products, pricing complex financial derivatives, resource allocation in 5G networks and financial portfolios. Current methods for addressing these problems are intensive, time-consuming, and expensive. The proposed chips would quantify the uncertainty and find suitable solutions to many real-world challenges with faster, cheaper, and more energy-efficient methods. This Small Business Technology Transfer (STTR) Phase I project focuses on advancing probabilistic computers for probabilistic computing. Decision-making, econometrics, risk management, chip design, and drug development are not deterministic. By leveraging the natural stochasticity of specific devices, it is possible to dramatically reduce the number of devices otherwise used for the same computational tasks. The proposed computational architecture and pipelining enables improved computational speed, power consumption, and chip manufacturing costs. The goals of this project are two-fold. The first is to deliver 10-1000x improvement in computation speed compared to CPUs and GPUs using the emulation of probabilistic computers on Field Programmable Gate Arrays. The same task will make projections about the performance of the actual probabilistic computer. The second is to quantify how well the probabilistic computer can accommodate semiconductor manufacturing process variations. Controlling such variations is a significant factor in semiconductor manufacturing costs. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Phase II

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Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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