SBIR-STTR Award

Dynamic Mode Adjustment Between High Performance and Power Saving States
Award last edited on: 5/14/2015

Sponsored Program
SBIR
Awarding Agency
NSF
Total Award Amount
$179,999
Award Phase
1
Solicitation Topic Code
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Principal Investigator
Agus Widjaja

Company Information

Packet Digital LLC

201 5th Street North Suite 1500
Fargo, ND 58102
   (701) 232-0661
   terri.zimmerman@packetdigital.com
   www.packetdigital.com
Location: Single
Congr. District: 00
County: Cass

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2014
Phase I Amount
$179,999
This Small Business Innovation Research (SBIR) Phase I project will research, design and demonstrate a new technique for dynamically controlling the operating mode for DRAM devices. Today memory is set to the highest performance and highest power mode at boot regardless of usage, an antiquated approach creating thermal hotspots and wasting power. The intellectual merit is a combination of both frequency and voltage scaling by monitoring activity to boost memory bandwidth under high demand conditions and resume lower frequency modes when higher performance is unnecessary. Traditionally, operating mode of memory is fixed at levels that will provide the peak performance required and is not modified while the system is running. The research objectives are to select a target architecture and platform, conceptualize dynamic mode switching by creating simulation models of the memory and determine minimum required supply voltages and frequencies, build an evaluation unit, and test and demonstrate activity-based dynamic mode switching. This dynamic mode concept will allow the memory to speed-up to complete activities sooner and optimize power consumption in real time providing both system and performance benefits for consumers and resulting in the world?s first dynamic real-time architecture for varying memory clock frequency and voltage based on activity. The broader impact/commercial potential of this project is significant power savings to address green energy initiatives and poor battery life across consumer, business, and military electronic market segments. This includes memory applications such as data center servers, notebooks, and extending battery life in handheld electronics. This technology will enable smaller, more flexible, and more easily integrated power management with an improved cost/benefit ratio. Commercially, annual memory module shipments are expected to reach over 1 billion units by 2014. With market penetration rate of 0.2% there is a commercial potential of $5 million in revenue in 2017 and $11 million by 2019. With this technology in their mobile devices the consumer will see reduced power consumption resulting in extended battery life, lower heat dissipation and cooling costs and increased reliability. Compared to statically assigning a power saving mode the consumer will see faster response to application starts and improved performance, throughput, and bandwidth while still saving power and costs during less demanding activities. This project is a truly unique project that has far reaching benefits for today?s handsets, tablets, PCs, and servers.

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
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Phase II Amount
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