SBIR-STTR Award

A Demonstration of an Intelligent IO-to-N Interface
Award last edited on: 10/25/2018

Sponsored Program
SBIR
Awarding Agency
DOD : Navy
Total Award Amount
$699,627
Award Phase
2
Solicitation Topic Code
N98-038
Principal Investigator
Martin H Davis Jr

Company Information

Icore Technologies

PO Box 31205
Dayton, OH 45437
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Location: Single
Congr. District: 03
County: Montgomery

Phase I

Contract Number: N68936-98-C-0147
Start Date: 5/13/1998    Completed: 11/13/1998
Phase I year
1998
Phase I Amount
$99,649
Today's network technologies easily reach 1 Gbit/sec bandwidths, but current IO board products based on these Gbit network technologies cannot harness that bandwidth. We have already developed an Intelligent IO-to-N (IION) interface. The IION interface allows any modern high-speed IO bus (e.g., PCI) to be interconnected to any modern Network protocol (e.g., SCI, Fibre Channel, ATM). The interface's onboard Intelligent hardware enables the IION board to deliver high delivered throughput, low latency, and flexible programming interfaces. Our IION board's architecture is unique because of the onboard intelligence that not only allows the board's configuration to be modified for specific IO buses, Network protocols, and new applications, but which incorporates new algorithms (which we have already invented) to increase its performance. For this effort, we propose to further the development of the IION architecture. First, we will build a complexity/cost/performance model of the IION architecture - this allows quick trade-off studies and rapid prototyping of new boards. Second, we will define a General-purpose Application Programming Interface - this enables general-purpose parallel programming in enterprise clustered workstation configurations. Third, we will demonstrate our existing IION board - this will show how the IION concept performs in the real world. Fourth, we will design an avionics-specific version of the IION board - this will demonstrate how the prior three results can be used to produce new variations of the IION board. At the end of Phase 1, we will be ready to begin the Phase 2 work of implementing the avionics-specific IION board.

Benefit:
There are two major commercial benefits. First, we will release into the public domain the General-purpose Application Programming Interface specification by starting the public standardization process of the spec. This will enhance and mature the market for parallel programming in enterprise clustered workstation configurations. Second, a high-performance (high delivered throughput, low latency, flexible protocol conversion) board for avionics will be designed, developed, and marketed. This will enable avionics designers to take advantage of new IO buses and Network protocols and to evolve the programming interface as the programming techniques evolve.

Keywords:
bus, bus, gigabit, API, clusters, intelligent, Avionics, Workstation, Network, IO

Phase II

Contract Number: N68936-99-C-0044
Start Date: 3/1/1999    Completed: 3/1/2001
Phase II year
1999
Phase II Amount
$599,978
The research and development of an intelligent, programmable, high-speed, low-latency

Benefit:
The iCoreLink board provides a high-performance, low-latency network interface card. It is constructed from commercial-off-the-shelf components, but because of its onboard intelligence, it can be customized to provide functionality for specific applications. It can also provide a consistent programming interface no matter what the network technology is. It will find application in clustered computing, fault-tolerant computing, Internet/Intranet servers, secure access networks, video and cable communications, digital video creation and manipulation, high-speed typesetting, and large-scale electronics test equipment, LAN and WAN switches, large-scale data warehouses, routers, telecommunication switches, and embedded data acquisition, simulation and control.

Keywords:
Workstation, Network, clusters, Avionics , API, gigabit, IO, intelligent, bus