Manufacturing Platform for High-Temperature CMOS ICs on SiC
Award last edited on: 6/24/22

Sponsored Program
Awarding Agency
Total Award Amount
Award Phase
Solicitation Topic Code
Principal Investigator
Adam Morgan

Company Information

Nomis Power Group LLC

22 Appletree Lane
Newtonville, NY 12110
   (518) 944-3910
Location: Single
Congr. District: 20
County: Albany

Phase I

Contract Number: HQ072721P0023
Start Date: 7/29/21    Completed: 2/10/22
Phase I year
Phase I Amount
This project aims to develop high-temperature (> 300°C) operational dielectrics for SiC CMOS integrated circuits (ICs) technologies in a production-grade fabrication facility in the U.S. All outcomes of this project will directly benefit future implementations of various kinds of high-temperature electronics for defense applications.Increasingly, the development of SiC CMOS-based ICs that can operate at high temperatures is at the forefront of SiC-based device research. Despite many technical barriers to achieving high temperature operation of SiC CMOS ICs, it is paramount that significant effort be devoted to the development of reliable dielectrics and credible fabrication sources for high-temperature SiC CMOS ICs. Benefiting from the current effort on SiC SMART IC (funded by ARPA-e, issues for SiC CMOS-based circuits when operating at high temperatures will be identified in the beginning of the project. The methodology for pursuing the proposed solutions in this project are unique in that: 1) New process schemes or methodologies will be developed at the proposed production-grade fabrication facility from the beginning, as solutions developed in small-scale cleanroom environments are often difficult to implement successfully in a volume manufacturing facility due to incompatibility; 2) Advanced capability and tool variety at the proposed facility will ensure successful demonstration of newly proposed process technology; 3) High-temperature operations of SiC CMOS-based exemplary circuits will be demonstrated as a goal of this project; 4) While focused on gate dielectric (µn > 50 cm2/V-s, µp > 10 cm2/V-s, Vth shift < ± 0.5 V) and interlayer dielectric (ILD) processes, other process-related developments such as ohmic contacts and packaging of the ICs will also be pursued for the functional demonstration of high-temperature SiC CMOS FETs; 5) The process baseline for SiC CMOS that is being established in an already existing project will be the basis of the proposed research, which will reduce effort/time for this project, ensuring the chance of succe

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
Phase II Amount