Innovating Cryo-CMOS PDKs and ICs
Award last edited on: 4/4/22

Sponsored Program
Awarding Agency
DOD : Army
Total Award Amount
Award Phase
Solicitation Topic Code
Principal Investigator
Philbert Marsh

Company Information

Carbonics Inc

4640 Admiralty Way #1015
Marina Del Rey, CA 90292
   (608) 262-3863

Research Institution

Georgia Institute of Technology

Phase I

Contract Number: W911NF-21-P-0032
Start Date: 12/11/20    Completed: 6/10/21
Phase I year
Phase I Amount
Carbonics will partner with Georgia Tech to innovate and develop DC/RF device models and RF integrated circuit CMOS prototypes for operation at deep cryogenic temperatures with superior performance with low power consumption and enhanced noise performance. Our approach will adopt state-of-the-art semiconductor technology that includes bulk CMOS, CMOS SOI, and FinFET. Our plan is to commercialize our Cryo-CMOS technology framework by partnering with a USA trusted foundry to enable first insertion DoD customers with our “cryo-CMOS” device models, circuits and PD

Phase II

Contract Number: W911NF-22-C-0039
Start Date: 4/14/22    Completed: 4/30/24
Phase II year
Phase II Amount
Within this Phase-II STTR program, Carbonics and Georgia Tech will develop cryogenic CMOS devices and circuits and support them with compact models valid from 4.2K to over 300K to enable applications such as quantum computer qubit readouts and radio astronomy. The developed compact models will be valid over both small and large-signal operation and will accurately model RF noise parameters. Current CMOS RF models are validated only down to -40C. However, there is strong interest in the development of CMOS circuits for cryogenic operation (4.2K) for applications such as qubit readouts for quantum computing and radio astronomy applications, particularly space-based radio telescopes. In this project, we will fabricate and demonstrate of a cryogenic CMOS low-noise amplifier operating in the band 2-3GHz. Cryogenic CMOS technology will also be used to demonstrate a low phase noise 10GHz oscillator and phase locked loop (PLL). In order to realise our technical deliverables, our team will fabricate discrete CMOS FETs using a maskset which allows complete deembedding of the intrinsic FET S-parameters from the surrounding structures such as probe pads and protection diodes. On-wafer calibration kits will be included as well as separate protection diodes and pads structures to allow determination of intrinsic FET S-parameters vs. bias and temperature.