SBIR-STTR Award

Frequency Domain Aiding Module And Frequency Domain Receiver For Fast Acquisition High Acceleration And Jam Resistance
Award last edited on: 5/20/02

Sponsored Program
SBIR
Awarding Agency
DOD : AF
Total Award Amount
$849,827
Award Phase
2
Solicitation Topic Code
AF98-164
Principal Investigator
James W Chaffee

Company Information

ZC&H Dynamic Systems Inc (AKA: Arrowsmith Technologies Inc~J Chaffee & Associates)

5608 Muster Court
Austin, TX 78713
   (512) 794-2804
   N/A
   N/A
Location: Single
Congr. District: 25
County: Travis

Phase I

Contract Number: F33615-98-C-1290
Start Date: 4/2/98    Completed: 1/15/99
Phase I year
1998
Phase I Amount
$99,979
The design and development of a digital signal processing based module to pre-process raw GPS data is proposed. Using frequency domain techniques to aid tracing loop, conventional receiver could maintain lock with narrow bandwidth at 90 g of acceleration and 90 g/s of jerk or more, as well as rapidly acquire the P(Y)-code directly. This technology has been studied and tested since the mid 1980s and is now ready for implementation as the next innovation in digital GPS. This approach also provides the ability to suppress jamming. This technology is also directly applicable to developing a fully DSP-based frequency domain GPS receiver for high dynamics and fast acquisition in jamming environments. Prototype receivers have been developed and tested for high dynamic tracking, and there was a frequency domain receiver for use on missiles developed and manufactured by a foreign nation. Frequency domain methods are also beginning t find there into new GPS receivers for fast, direct P(Y)-code acquisition in a jamming environment. However, there is a not single receiver that combines all these properties into a single unit, and this is proposed here as a follow on to the preprocessor, which would be a module the full receiver.

Keywords:
Fast Fourier Transform Digital Signal Procesing Direct P(Y)-Code Acquisition Time-Frequency Localiza

Phase II

Contract Number: F33615-99-C-1429
Start Date: 3/25/99    Completed: 3/25/01
Phase II year
1999
Phase II Amount
$749,848
We propose to continue our Phase I effort by developing a prototype DSP-based GPS aiding module and receiver component that will rapidly acquire P-code without the need of C/A-code, that is will directly acquire p(Y)-code with large time uncertainties. The prototype will able to acquire under jamming conditions. Moreover, it will track carrier phase while under extremely high dynamics of 100 Gs or more. The prototype will serve as model for either an aiding unit for conventional receivers or as a component of a P(Y)-code receiver. The prototype will be an extended RF front-end with down conversion, a DSP processor, and a Pentium-based PC. This platform will not only provide our prototype but will also serve as a test bed for other DSP-based P(Y)-code GPS receiver algorithms since the all the software will be accessible and suitable for modification.

Keywords:
Fast Fourier Transform Gps P(Y)-Code Carrier Phase Digital Signal Processing Direct Acquisition Freq