SBIR-STTR Award

Signal and information processing advancements are the backbone of key enabling technologies for decisive overmatch on the battlefield. Progress specifically in digital signal processing (DSP) methods directly impacts Long Range Precision Fires and Air and Missile Defense Army Modernization Priorities. With each new generation of sensors, the requirements of these processing capabilities must also advance, and it is unclear if conventional DSP can continue to rise to the challenge within such constrained environments, where the available size, weight, power, and cost (SWaP-C) are limited. In this effort, IERUS Technologies and its partners will design and implement unclocked signal processing blocks in a reconfigurable platform with reduced power consumption when compared to conventional DSP. To do so, the team will combine three existing research fields from signal processing: (i) asynchronous analog-to-digital converters (ADCs), (ii) asynchronous Field Programmable Gate Arrays (FPGAs), and (iii) Continuous-Time Digital Signal Processing (CTDSP). Our efforts will target the development of unclocked modules that work with/alongside existing DSP operations. Our primarily focus will be maturing FPGA-based CTDSP modules with the development of designs and methodologies that are vendor agnostic and capable of replacing and/or complementing DSP blocks.

Modern missile systems require tremendous amounts of signal and information processing using constrained resources in an extreme environment. Multi-spectral sensors, high-bandwidth communications, and supersonic flight control demand significant processing power, while space and weight constraints limit available power and heat dissipation. It is uncertain that conventional Digital Signal Processing (DSP) approaches can provide the increased performance required in next generation missile systems. To meet this need, alternatives to conventional, power-hungry digital processing approaches are desired. The effort proposed here continues the investigations and implementation of a promising novel approach in continuous-time digital signal processing (CTDSP), which achieves similar or improved performance while potentially offering a significant decrease in power and heat dissipation requirements. These algorithms have been implemented on reconfigurable hardware, field programmable gate arrays (FPGAs) to enable the flexible design of future systems. During the phase II effort, the development team will advance the Phase I results by refining the developed CTDSP blocks and design methodologies in order to create robust architectures to operate across an abundance of FPGAs and application scenarios. Throughout this refinement, the team will continue to develop practical implementation and parameter recommendations that fall for flexible integration based on user needs.