SBIR-STTR Award

A High Performance 90nm ‘Schottky’ CMOS Process for Mitigation of Parasitic Bipolar Effects and Dramatically Reduced Bit Upset Rates
Award last edited on: 4/21/2014

Sponsored Program
SBIR
Awarding Agency
DOD : AF
Total Award Amount
$849,401
Award Phase
2
Solicitation Topic Code
AF103-087
Principal Investigator
John P Snyder

Company Information

Avolare 2 LLC

112 Ellsworth Place
Chapel Hill, NC 27516
   (919) 539-8821
   john.p.snyder@gmail.com
   N/A
Location: Single
Congr. District: 04
County: Orange

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2011
Phase I Amount
$99,401
Avolare 2, LLC proposes the simulation and quantization of single event effects (SEUs) on highly scaled (i.e., sub-65 nm gate length) metal source/drain "Schottky" CMOS (SB-CMOS) transistors. Mixed-mode 2D device/circuit simulations of an SRAM core (back-to-back inverters) subjected to an energetic particle strike will be modeled. Avolare 2’s proprietary Monte Carlo TCAD tool ‘WhiteCap’ will be used to model the inverter not affected by the strike (a SPICE-like circuit simulation using compact models) and will also perform full 2D device-level simulations of the inverter subjected to ionizing radiation. N and p type devices, metal and conventional doped source/drain structures, gate lengths from 65nm to 10nm and uniformly doped well and double well (buried p-n junction) architectures will be investigated. The threshold LET – the minimum LET that causes upset – will be determined for each combination of parameters. Comparison/plots of threshold LET for metal and conventional doped source/drain structures with device type, gate length and well structure as parameters. Determination of threshold LET advantage of metal source/drain vs doped source/drain structure

Benefit:
The successful development of rad-hard metal source/drain "Schottky" CMOS (SB-CMOS) technology and the quantization of single event effects on SB-CMOS will be of great benefit to many system designers (military and commercial alike) who require highly scaled, high-performance components with the capability to operate reliably in radiation laden environments. Furthermore, due to the outstanding performance of SB-CMOS for high-speed, low-power applications, SB-CMOS based integrated circuits have the ability to enable entirely new classes of consumer and commercial products and will likely find widespread adoption across the electronics industry.

Keywords:
Radiation Hardened, Rad Hard, Metal Source/Drain Cmos, Schottky Cmos, Single Event Upset, Seu, Single Event Effects, Highly Scaled

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
2013
Phase II Amount
$750,000
Avolare2 proposes to establish a 90nm metal source/drain ‘Schottky’ CMOS process at Cypress Semiconductor’s high volume manufacturing facility in Bloomington, MN. Schottky CMOS will have a profound impact on the performance and reliability of most of the integrated circuits (ICs) providing critical functionality for electronic systems operating in high radiation environments. The Schottky process flow will be based on an existing conventional 90nm process already in production at Cypress. Development of high-performance digital and mixed-signal components by the design community will allow for greater levels of machine-intelligence in spacecraft, aircraft, and missile applications. Schottky CMOS is 100% compatible with current CMOS process equipment and requires fewer process steps, providing military IC suppliers with a convenient path to upgrade existing fabrication lines and offer ICs with latch-up and single event upset (SEU) immunity at faster speeds and lower power consumption. The Schottky transistor’s performance and SEU immunity benefits are expected to become even more pronounced at advanced linewidths (45nm and below), ushering in a new era of component innovation for military and commercial systems alike, accelerating adoption by commercial IC foundries and enabling the development of novel computing, communication, and consumer electronic products.

Benefit:
Space-based systems and avionics applications require highly integrated, cost-effective, state-of-the-art integrated circuits (ICs) capable of withstanding harsh radiation laden environments. Scaling conventional semiconductor transistors from 2000 nm to 150 nm provides the IC with speed-power-cost benefits, but the traditional transistor becomes more susceptible to radiation effects at smaller geometries. The successful development of rad-hard, metal source/drain Schottky-barrier CMOS (SB-CMOS) technology will enable military IC suppliers to take advantage of the performance benefits of advanced circuit geometries (90 nm and below) without sacrificing reliability due to radiation effects, providing defense and aerospace system contractors access to the critical high-performance components with minimum power, size, weight, and cost.

Keywords:
Radiation Hardened, Rad Hard, Metal Source/Drain Cmos, Schottky Cmos, Single Event Upset, Seu, Single Event Effects, Planar Bulk