Throughout the history of integrated circuit fabrication, gate stack engineering has been employed to meet the aggressive device scaling necessary to stay on the Moores Law curve. However, as device dimensions continue to progress into the sub-100-nm regime, scaling of the traditional SiO2 gate dielectric led to issues with reliability, dopant penetration and excessive gate leakage current. Overall, these issues have culminated with the abandonment of SiO2/polysilicon-based systems altogether starting as early as the 45-nm generation of process technologies. At this node, several companies intend to introduce high-k/metal-gate systems. In order to search this complex space effectively, a new type of PVD deposition tool is required. Although this tool is ideal for depositing the comprehensive arrays of materials necessary to address the work function engineering problem, the productivity of the tool in this application is limited by the lack of in-situ, non-contact diagnostics that enable the characterization of each material immediately following the material deposition in a throughput-matched manner. We seek to develop and integrate these sensors in this SBIR program.
Keywords: Semiconductor In-Line Electrical Test, Combinatorial
